In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become impractical for several reasons. One of the problems in utilizing solder paste screening technique in bonding modern semiconductor devices is the paste composition itself. A solder paste is formed by a flux material and solder alloy particles. The consistency and uniformity of the solder paste composition become more difficult to control as the solder bump volume decreases. Even though a solution of the problem has been proposed by using solder paste that contain extremely small and uniform solder particles, it can only be achieved at a high cost penalty. A second problem in utilizing the solder paste screening technique in modern high density semiconductor devices is the available space between solder bumps. It is known that a large volume reduction occurs when a solder changes from a paste state to a cured stated, the screen holes for the solder paste must be significantly larger in diameter than the actual solder bumps to be formed. The large volume shrinkage ratio thus makes the solder paste screening technique difficult to carry out in high density devices.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1A.about.1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion diffusion barrier layer 30 and a wetting layer 28. The adhesion diffusion barrier layer 30 may be formed of Ti, TiW or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UMB layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UMB layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 .mu.m and about 40 .mu.m, preferably at a thickness of about 35 .mu.m. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 42. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
The conventional method for depositing solder bumps described above presents a number of processing difficulties. For instance, one of the difficulties is the large volume of solder used in a mushroom-shaped bump which impedes the process of making fine-pitched bumps. The other processing difficulties are the complexity of the method and the large number of processing steps required. For instance, FIG. 2 illustrates, on the left side of the figure, the processing steps required for a conventional flip chip bonding method. First, the IC chip is prepared by forming aluminum bond pad on the chip, followed by an under-bump-metallurgy (UBM) process for preparing bonding sites for solder bumps, and then the solder bumping or bump forming process by electrodeposition, electroless deposition, etc. The substrate must also be prepared by coating a flux coating layer on top of the conductive elements that the solder bumps are bonded to. The flip chip bonding process is then carried out by pressing the solder bumps on the IC chip against the conductive elements on the substrate together forming bonds, the solder bumps are then reflown to ensure ohmic contacts are established between the solder bump and the conductive elements. The solder bumps on the IC chip may optionally be coated with a flux coating layer by a fluxer (or a doctor plane). A flux cleaning step is then required to remove the excess flux coating on the substrate followed by a drying step for removing the cleaning solvent. In the final steps of the flip chip bonding process, an underfill material is used to fill the gaps between the IC chip and the substrate for passivation and for relieving thermal stresses, followed by a curing or annealing process for the underfill layer. As shown in FIG. 2, there are at least ten major processing steps required in the conventional flip chip bonding method to complete a flip chip package.
It is therefore an object of the present invention to provide a method for forming a flip chip package that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming a flip chip package by utilizing cone-shaped solder bumps formed on an IC chip.
It is a further object of the present invention to provide a method for forming a flip chip package by using cone-shaped solder bumps that are equipped with sharp-pointed tip portions for penetrating an electrically insulating material layer positioned in-between the IC chip and a substrate.
It is another further object of the present invention to provide a method for forming a flip chip package by utilizing cone-shaped solder bumps formed on an IC chip of a solder material such as Sn/Pb, Sn/Zn or Sn/Ag.
It is still another object of the present invention to provide a method for forming a flip chip package by utilizing cone-shaped solder bumps provided on an IC chip and heating an electrically insulating material layer positioned in-between the IC chip and a substrate to a temperature of at least 150.degree. C. for bonding the solder bumps to the conductive elements on the substrate.
It is yet another object of the present invention to provide a method for forming a flip chip package by using cone-shaped solder bumps on an IC chip and a dielectric material layer having a thickness between about 10 .mu.m and about 250 .mu.m between the IC chip and a substrate wherein the solder bumps penetrate the dielectric material layer establishing electrical communication with conductive elements on the substrate.
It is still another fierier object of the present invention to provide a flip chip package formed by cone-shaped solder bumps that are equipped with sharp-pointed tip portions and an electrically insulating material layer between an IC chip and a substrate.
It is yet another further object of the present invention to provide a flip chip package that utilizes an electrically insulating material layer between an IC chip and a substrate wherein the layer is a laminate with a dielectric core layer sandwiched between two layers of electrically insulating adhesive material.